1. Technical Field
The present invention relates to a test apparatus and a test method for testing a device, and to a manufacturing method for manufacturing a device.
2. Related Art
A known apparatus for testing a plurality of devices formed on a semiconductor wafer uses a probe card that can contact a large number of electrodes of the wafer en bloc (see Patent Document 1). This apparatus is placed in an analyzing device while the probe card is in contact with the wafer under test, and analysis is performed at a high temperature, for example. Patent Document 2 describes an apparatus that houses chips in a package that is the same as the commercial package, and tests the chips in this state.    Patent Document 1: Japanese Patent Application Publication No. 2006-173503    Patent Document 2: Japanese Patent No. 4122102
However, in each of the above apparatuses, a large number of wires must be connected to manufacture the probe card, and this incurs a high cost. Furthermore, it is difficult to adjust the relative positions of the wafer under test and the probe card. When testing chips after dicing that are housed in a package that is the same as the commercial package, the package configuration is complicated and the cost of the package is high.